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University program for GateMate FPGA family

26/05/2023

Cologne Chip opens a new chapter for its GateMate FPGA family by introducing University Program, which significantly reduces the entry barrier into FPGA field for students, researchers and lecturers. Cost effective, high performance and open-source design flow, give an excellent opportunity for academia around the globe to start implementation of new ideas in GateMate FPGAs. The application for University Program is simple and the tools and evaluation boards are on stock and available immediately.

The GateMate A1 FPGA is the smallest-dimensioned component of the GateMateTM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.

Main Features

GateMateTM FPGA Features

Novel CPE Architecture

  • 20,480 programmable elements (CPE) for combinatorial and sequential logic
  • 40,960 Latches / Flip-Flops within programmable elements
  • CPE consists of LUT-tree with 8 inputs
  • Each CPE configurable as 2-bit full-adder or 2x2-bit multiplier

Low Power Consumption

  • GlobalfoundriesTM 28 nm SLP (Super Low Power) process
  • 3 operation modes: low power, economy, speed
  • No excessive start-up currents
  • Only two supply voltages needed, can be applied in any order

Features

  • 4 programmable PLLs
  • Fast configuration with quad SPI interface up to 100 MHz
  • Multi-Chip configuration
  • 1,280 Kbit dual ported block RAM with variable data widths in 32 x 40 Kbit RAM cells
  • Multipliers with arbitrary size implementable in CPE array
  • Multiple clocking schemas
  • All 162 GPIOs configurable as single-ended or LVDS differential pairs
  • Double data rate (DDR) support in all GPIO cells
  • 5 Gb/s SerDes

Package

  • 324-ball BGA package (15x15 mm)
  • Only 2 signal layers required on PCB
Documents Tech question
Cologne chip Gate Mate CCGM1 A1 FPGA

University program for GateMate FPGA family

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Cologne Chip

Cologne Chip follows the latest developments in broadband access technologies, providing its ISDN transceivers to all kinds of Residential Gateways for the Central European market.

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Documents

  • Cologne Chip FPGA University Program
Pexels thisisengineering 3913017

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